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Senior RTL Design Lead

HCLTech·Bengaluru

Pay not stated5–7 yrsFull-time
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About the role

Candidates with 5 to 7 years experience is mandatory Static Timing Analysis closure, resolving P& R congestion issues etc. Experience integrating IP's like PCIe, USB, Ethernet etc.

What you need

  • 5–7 yrs of experience
  • Verilog
  • VLSI
  • Any graduate

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