Senior Silicon Engineer, HBM Memory Subsystem Design, Integration and Validation

About the role

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU.

What you'll do

• Define microarchitecture and develop high-quality RTL for memory controller frontends, guiding implementation trade-offs across performance, area, power, timing
• Lead the design, integration, and delivery of complex memory controller backends and HBM/DDR PHY macros, owning quality closure (DFI pipe wrappers, clock/reset
• Collaborate with DV teams to build test plans, improve coverage, and validate design intent (UVM, emulation, ECC/RAS error injection)
• Lead and support ATE testing, first-silicon lab bring-up, and physical characterization of the HBM PHY and controller across PVT (process, voltage, temperature) corners
• Provide technical guidance and mentoring to engineers while promoting best practices in RTL design, review, documentation, methodology, and systematic root-cause debug

What you need

• 10–18 yrs of experience
• Verilog
• UVM
• VLSI
• VBA
• Test cases
• Machine learning
• B.Tech or B.E. or PhD

Good to have

• GCP