Senior Solution Architect

About the role

This role requires deep expertise in system-level verification, integration challenges, and leadership across multiple IP/block teams.

What you'll do

• Own end-to-end chip-level DV from planning to signoff
• Define and drive verification strategy, including reuse of block-level environments
• Ensure functional correctness of integrated SoC across all subsystems
• ������ Testbench & Methodology
• Architect and develop scalable chip-level testbenches (typically UVM-based)

What you need

• 12–18 yrs of experience
• UVM
• FPGA
• Verilog
• Root cause analysis
• Any graduate

Good to have

• Python
• Prototyping
• Perl