Senior STA Engineer

About the role

We are looking for a Senior STA Engineer with strong expertise in Static Timing Analysis, timing signoff, and timing closure for complex ASIC/SoC designs. The candidate will own timing analysis activities across the design flow and work closely with RTL, Synthesis, Physical Design, and Signoff teams to resolve complex timing issues.

What you'll do

• Own STA and timing signoff activities from synthesis through physical design and tape-out
• Perform MCMM/MMMC timing analysis across all functional and test modes
• Analyze and debug setup, hold, recovery, removal, min/max, and clock-related violations
• Develop, review, and validate SDC constraints , including clocks, generated clocks, I/O delays, false paths, multicycle paths, and timing exceptions
• Perform detailed clock tree and clock timing analysis , including skew, latency, uncertainty, jitter, and clock reconvergence

What you need

• 6–11 yrs of experience
• VLSI
• Python
• B.Tech or B.E. or M.Tech

Good to have

• Perl