Senior Staff AMS Design Verification Engineer

About the role

Senior project lead of a team of engineers in the tasks of guaranteeing specification compliance of analog & mixed signal design by means of advanced verification methodologies and concepts. It involves definition, deployment, and improvement of state-of-the-art verification methodologies.

What you'll do

• Take responsibility for design verification to achieve first pass silicon success and to ensure design meets performance, power, and timescale constraints
• Lead analog & mixed signal verification of complex integrated circuits or sub-systems
• Provide a technical interface between AMS DV teams and any local contract DV resources
• Develop verification strategy for mixed signal IPs and implement the verification IP following object-oriented programming principles and methodologies including UVM
• Develop efficient, reusable state-of-the-art verification environments and testbench structures

What you need

• 10–18 yrs of experience
• Verilog
• UVM
• VLSI
• Shell scripting
• Perl
• Maintenance
• B.Tech or B.E.

Good to have

• Performance management
• Talent management