Senior /Staff AMS Layout engineer-DPG-LPDDR

About the role

Own and drive custom analog and mixed-signal layout for critical LPDDR PHY blocks, including Datapath, bias networks, IO front ends, and reference circuits, ensuring robust operation across PVT, low noise coupling, and high matching accuracy

What you'll do

• Own and drive custom analog and mixed-signal layout for critical LPDDR PHY blocks, including Datapath, bias networks, IO front ends, and reference circuits
• Lead high-speed LPDDR (LPDDRx) interface layout execution , solving complex signal integrity challenges such as skew control, impedance matching, shielding
• Architect and implement scalable array-based layout strategies for DQ/DQS byte lanes, CA lanes, and replica paths, ensuring strict symmetry, pitch matching
• Drive integration of custom digital and mixed-signal blocks within the PHY (training logic, calibration engines, test/debug circuitry), ensuring optimal clocking
• Lead layout-aware co-design with circuit teams , enabling early closure of timing, noise, IR, EM, and parasitic effects

What you need

• 3–12 yrs of experience
• Power systems
• Python
• Calibration
• Machine learning
• Chartered Accountant