Senior Staff ASIC Design Verification Engineer

About the role

Senior Staff ASIC Design Verification Engineer at MaxLinear. We are looking for a Senior Staff ASIC Design Verification Engineer to lead complex verification execution and contribute significantly to IP, Subsystem.

What you'll do

• Lead and execute verification activities at the IP, Subsystem, and SoC levels
• Define verification test plans and contribute to overall verification strategy
• Develop, enhance, and maintain reusable UVM-based verification components and environments
• Drive functional and code coverage closure and debug complex verification issues
• Own key verification deliverables from development through sign-off

What you need

• 8–12 yrs of experience
• VLSI
• UVM
• Verilog
• C++
• C
• Python
• B.Tech or B.E.

Good to have

• Linux
• Perl
• Test cases