Senior Staff Design Verification Engineer

About the role

The Senior Staff Design Verification Engineer is a senior technical contributor within the Smart Analog and Sensors responsible for delivering high-quality verification solutions for complex System-on-Chip (SoC) products. This role drives verification planning, methodology development, testbench architecture, functional validation, coverage closure, and debug activities across multiple subsystems and full-chip designs.

What you'll do

• Develop and maintain advanced UVM-based verification environments for complex SoC and subsystem-level designs
• Define comprehensive verification plans based on architecture and design specifications
• Create reusable verification infrastructure, agents, scoreboards, monitors, and checkers to support multiple projects
• Develop constrained-random and directed test scenarios to validate functionality and corner-case behavior
• Verify processor, memory, interconnect, sensor, and peripheral subsystems at both block and SoC levels

What you need

• 8–14 yrs of experience
• Verilog
• UVM
• VLSI
• Python
• Perl
• Test cases
• B.Tech or B.E. or M.Tech or PhD

Good to have

• FPGA
• CI/CD
• Prototyping