Senior Staff Design Verification Engineer SOC

About the role

We are looking for a St Staff Engineer with hands-on development of testbenches, testcases and checkers to exercise and measure design behavior against specified intent.

What you'll do

• Debug differences in simulated behavior of designs and design specifications
• Contribute to the development of DV flows and methodology for improved development efficiency. Independently manage verification tasks while mentoring junior team members
• Collaborate with cross-functional teams (Spec, Design, etc) to resolve bugs

What you need

• 8–10 yrs of experience
• UVM
• Verilog
• Python
• Perl
• B.Tech or B.E. or B.Sc or BCA