Senior Staff Digital Design Engineer

About the role

Develop micro-architecture and front-end digital design deliverables from concept to silicon with minimal supervision Develop digital functional blocks for various power management ASICs

What you'll do

• Lead optimized digital blocks design meeting functional and low power constraints and ensure spec compliance
• Must be able to handle Clock Domain Crossing across multiple clock domains seamlessly and in a glitch free manner
• Should be able to lead/collaborate for Logic Synthesis, Formal verification, Power estimation and STA
• Should be an expert of one or more Power Chip Communication I/Ps and protocols e.g. I2C, PMBUS etc
• Verification test planning, feature extraction and verification test case development

What you need

• Verilog
• Test cases
• Root cause analysis
• B.Tech or B.E.