Senior Staff Engineer Design

About the role

This role offers the opportunity to drive verification excellence using SystemVerilog, UVM, AMBA protocols, CDC/RDC analysis, and coverage-driven methodologies while collaborating with experienced engineering teams. Your role Key responsibilities in your new role Develop and execute verification plans for WLAN MAC digital designs and subsystems.

What you'll do

• Develop and execute verification plans for WLAN MAC digital designs and subsystems
• Build, enhance, and maintain SystemVerilog/UVM based verification environments and testbenches
• Create test plans, test cases, verification scenarios, and verification documentation
• Develop and integrate Verification IPs (VIPs) for protocols such as AMBA (AXI/AHB/APB) and PCIe
• Drive functional, code, assertion, and coverage closure activities

What you need

• 8–14 yrs of experience
• UVM
• Verilog
• Test cases
• Root cause analysis
• Customer success
• B.Tech or B.E. or M.Tech