Senior Staff Engineer Design

About the role

We are looking for an experienced RTL Design Engineer who can drive the complete design cycle from specification to micro-architecture, RTL implementation, and quality sign-off while optimizing for Power, Performance, and Area (PPA). This is an opportunity to work closely with architecture, verification, and implementation teams on cutting-edge SoC/IP development.

What you'll do

• Own the RTL design cycle from specification analysis to micro-architecture definition and RTL implementation
• Develop detailed micro-architecture documents from high-level product specifications
• Translate architecture and design requirements into high-quality RTL using Verilog/SystemVerilog
• Collaborate with architecture teams to review and refine design and micro-architecture proposals
• Deliver RTL that is functionally correct and optimized for Power, Performance, and Area (PPA)

What you need

• 8–14 yrs of experience
• Verilog
• VLSI
• Customer success
• B.Tech or B.E. or M.Tech