- Can I apply
- Needs PhD or B.Tech or B.E. · 7–13 yrs
- Pay
- Pay not stated
- Source
- From the company's careers page · today
- How to apply
- On Cisco's site: account needed, ~10–15 min
Early: posted 1 h ago on their own site
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About the role
#WeAreIn to transform theoretical concepts into real hardware designs. Are you in?
What you'll do
- Key responsibilities in your new role
- Develop micro-architecture and RTL coding for IP development in system Verilog/Verilog
- Work with the stakeholders and manage the digital IP roadmap
- Perform comprehensive quality checks to ensure robustness and accuracy of IP design including Lint, CDC, RDC, synthesis, DFT checks, ATPG
- Technically lead and mentor the juniors working with you
What you need
- 8–14 yrs of experience
- Verilog
- VLSI
- Python
- Customer success
- Linux
- PowerPoint
- B.Tech or B.E.
Good to have
- Git
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