Senior Staff Engineer, Design Verification (Power & Analog IC's)

About the role

We are looking for a motivated and talented Digital Design Verification Engineer to join our team in creating next-generation Power management solutions.

What you'll do

• Define and own verification plans, methodologies, and coverage strategies for complex SoC designs
• Architect and implement verification environments from scratch and enhance existing frameworks
• Drive block-level, subsystem-level, and full-chip verification
• Build Agents, sequences, drivers, monitors, and scoreboards as part of automation
• Integrate industry-standard VIPs, create custom transactor

What you need

• 12–22 yrs of experience
• UVM
• Python
• C++
• Verilog
• C
• Test cases
• B.Tech or B.E.

Good to have

• Perl