Senior Staff Engineer - DFT

About the role

Responsible for SoC DFT Architecture definition/implementation/verification/silicon debug of SoC/Full Chip Responsible for ATPG, DRC analysis, Test coverage debug, Memory BIST implementation and verification Owner ship of JTAG/BSCAN/iJTAG, P1500 implementation and verification, Stuck at/TDF/Bridging/Cell-aware/iddq fault models

What you'll do

• Responsible for SoC DFT Architecture definition/implementation/verification/silicon debug of SoC/Full Chip
• Responsible for ATPG, DRC analysis, Test coverage debug, Memory BIST implementation and verification

What you need

• 12–22 yrs of experience
• VLSI
• Customer success
• B.Tech or B.E. or M.Tech

Good to have

• Python
• Perl