Senior Staff Engineer, Physical Design

About the role

With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub, our division’s (India for India) mission is to grow India market. We aspire to create products (SoCs, Software, Power and Analog chips etc) which serve needs for local market.

What you'll do

• Lead block- and subsystem-level physical design closure, including timing closure, congestion mitigation, power integrity, and overall physical implementation quality
• Collaborate closely with SoC-level physical design teams to align on clocking strategies, floorplanning intent, and integration requirements
• Apply deep understanding of clocking methodologies to ensure subsystem-level clock domains integrate cleanly into the broader SoC clock architecture
• Develop, refine, and scale subsystem closure methodologies, flows, and automation, improving predictability, quality, and execution efficiency
• Mentor and guide physical design engineers within subsystem teams, promoting best practices, technical rigor, and methodology adoption

What you need

• 7–13 yrs of experience
• VLSI
• Python
• Perl
• Verilog
• B.Tech or B.E. or M.Tech