Senior Staff Engineer Verification

About the role

We are hiring an experienced Senior Verification Engineer with 7+ years of expertise in ASIC/SoC Functional Verification . The ideal candidate will have strong hands-on experience in System Verilog/UVM , verification of DSP and arithmetic data paths , and integrating MATLAB/C reference models for RTL correlation.

What you'll do

• Develop and own System Verilog/UVM-based verification environments , including scoreboards, sequences, RAL, regressions, and coverage closure
• Verify DSP and arithmetic datapath blocks such as filters, transforms, sensor-processing, and measurement-chain subsystems
• Integrate C/MATLAB reference models using DPI and drive automated RTL-to-model correlation
• Perform regression management, failure triage, root-cause analysis, and verification sign-off activities
• Support silicon bring-up and collaborate with design teams to resolve functional issues

What you need

• 7–13 yrs of experience
• MATLAB
• UVM
• Verilog
• C
• Root cause analysis
• Customer success
• Any graduate