Senior Staff Interface IP Verification Engineer (Pre-Silicon- PCIe/CXL/DDR/Ethernet)

About the role

Senior Staff Interface IP Verification Engineer (Pre-Silicon- PCIe/CXL/DDR/Ethernet) at Synopsys (incl. Ansys). Own end-to-end verification of Interface IP blocks including PCIe, CXL, DDR, and Ethernet, from architecture review through silicon signoff.

What you'll do

• Own end-to-end verification of Interface IP blocks including PCIe, CXL, DDR, and Ethernet, from architecture review through silicon signoff
• Build and evolve UVM-based verification environments that are reusable across product lines and scalable for future protocol generations
• Define verification strategies and test plans that account for protocol compliance, performance corner cases, and system-level integration scenarios
• Develop constrained-random, coverage-driven test scenarios using SystemVerilog and UVM, targeting functional coverage closure and signoff quality
• Collaborate with architecture, design, firmware, and systems teams to identify and resolve issues early in the development cycle

What you need

• 8–14 yrs of experience
• UVM
• Verilog
• Test cases
• M.Tech or B.Tech or B.E.