Senior Staff Verification Engineer

About the role

Perform and supervise detailed Simulation, verification and validation of integrated circuits. Develop testbenches using System Verilog and UVM for functional and power aware RTL Develop UVM components like agents (active and passive), scoreboards and environments etc., develop assertions, functional coverage.

What you'll do

• Perform and supervise detailed Simulation, verification and validation of integrated circuits
• Develop testbenches using System Verilog and UVM for functional and power aware RTL
• Develop UVM components like agents (active and passive), scoreboards and environments etc., develop assertions, functional coverage
• Develop test plans, UVM based test sequences, layered sequences, virtual sequencers
• Drive closure of verification metrics to cover verification space. Work with the team to identify and close gaps in functional, power aware

What you need

• 8–14 yrs of experience
• UVM
• Verilog
• Test cases
• JIRA
• Customer success
• Jenkins
• B.Tech or B.E.

Good to have

• Git