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Senior Technical Architect

HCLTech·Bengaluru

Pay not stated8–14 yrsFull-time

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About the role

Candidates with 8 to 14 years experience is mandatory Has participated in multiple ASIC/SoC verification till tapeout stage 1.Experience in ASIC/SoC Testbench definition 2.Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM)."

What you'll do

  • Own and execute verification closure
  • Test case development, coding, execution, bug analysis

What you need

  • 8–14 yrs of experience
  • Python
  • UVM
  • Verilog
  • Perl
  • VLSI
  • Shell scripting
  • B.Tech or B.E.

Good to have

  • Test cases
  • C

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