Senior Technical Manager

About the role

The role needs strong constraint understanding, path-level debugging, timing-model awareness and the ability to translate analysis into implementable ECO actions.

What you'll do

• Perform STA and timing signoff using PrimeTime and/or Tempus
• Analyse setup, hold, recovery/removal, clock-gating and other relevant timing checks
• Debug interface timing, block-to-block paths, clock interactions and constraint-quality issues
• Build, validate and use timing models for hierarchical analysis where applicable
• Analyse OCV/AOCV/POCV, SI/crosstalk and parasitic effects on timing convergence

What you need

• 5–10 yrs of experience
• VLSI
• B.Tech or B.E. or M.Tech

Good to have

• Python