Senior Verification Engineer

About the role

Bangalore, Karnataka, India; Bengaluru, Karnataka, India

What you'll do

• Architect multi-agent UVM environments for a wide-issue VLIW pipeline (fetch, decode, hazard detection, execution units, in-
• Build equivalence scoreboards: SystemVerilog RTL vs. C/C++ cycle-accurate ISS, integer and IEEE-754 FP
• Develop constrained-random assembly generators for 100% ISA and register-file coverage across a large custom opcode
• Write SVA and drive formal property verification for arithmetic pipelines (fixed/float FMA, matrix multipliers, CORDIC
• Verify a compiler/hardware worst-case-timing contract (measured vs. claimed latency)

What you need

• 5–12 yrs of experience
• C++
• Verilog
• UVM
• C
• Any graduate