Senior Verification Engineer - HSIO Unit Level

About the role

During the course of a project, you will drive the following aspects of verification for your unit: Architect the testbenches and craft verification environment using SV and UVM methodology Define test plans, tests and verification infrastructure for modules, clusters and systems

What you'll do

• Architect the testbenches and craft verification environment using SV and UVM methodology
• Define test plans, tests and verification infrastructure for modules, clusters and systems

What you need

• 6–10 years in electrical & electronics
• UVM
• Test cases
• Any graduate

What you get