Senior Verification Engineer

About the role

The Verification Engineer will define verification architecture, implement verification environment for block level, SoC subsystems and SOC top level design that use advance verification methodologies and meet established content, performance, quality, cost and schedule goals. He/She will also be responsible for the simulations of the SOC

What you'll do

• Define overall verification strategies, methodologies, and simulation environment
• Work with RTL designers, system architects and block level verification engineers to develop top level verification requirements and test plans based on specifications
• Develop, maintain and publish verification specifications
• Analyze and debug simulation failures
• Generates code coverage and functional coverage report

What you need

• 3–6 yrs of experience
• Verilog
• UVM
• Python
• Test cases
• Perl
• Linux
• B.Sc or M.Sc