- Can I apply
- Needs PhD or B.Tech or B.E. · 7–13 yrs
- Pay
- Pay not stated
- Source
- From the company's careers page · today
- How to apply
- On Cisco's site: account needed, ~10–15 min
Early: posted 1 h ago on their own site
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About the role
SMMU Senior Lead Design Verification Engineer at Qualcomm. Ownership of DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage).
What you'll do
- Ownership of DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage)
- Develop test plan and test cases to cover design feature set, follow up with stake holders on code coverage, functional coverage closure at different levels of test bench
- Work closely with System Architects, Design, emulation teams on failure debugs, code/functional coverage closure
- Debug of regression signatures and identifying bug fixes
- Developing/Deploying scripts/tools for validation (Certitude, VC Formal, Fishtail)
What you need
- 3–6 yrs of experience
- UVM
- Verilog
- Test cases
- B.Sc or B.Tech or B.E. or BCA or M.Sc or M.Tech or MCA
Similar jobs
- Can I apply
- Needs PhD or B.Tech or B.E. · 7–13 yrs
- Pay
- Pay not stated
- Source
- From the company's careers page · today
- How to apply
- On Cisco's site: account needed, ~10–15 min
Early: posted 1 h ago on their own site
- Can I apply
- Needs PhD or B.Tech or B.E. · 7–13 yrs
- Pay
- Pay not stated
- Source
- From the company's careers page · today
- How to apply
- On Cisco's site: account needed, ~10–15 min
Early: posted 1 h ago on their own site
- Can I apply
- Needs PhD or B.Tech or B.E. · 7–13 yrs
- Pay
- Pay not stated
- Source
- From the company's careers page · today
- How to apply
- On Cisco's site: account needed, ~10–15 min
Early: posted 1 h ago on their own site