SOC Design Verification Engineer

About the role

We are seeking a highly motivated SoC Verification Engineer to support the verification of complex System-on-Chip (SoC) designs. The role involves developing and executing verification plans, building robust verification environments, and debugging functional issues to ensure design quality, performance, and reliability.

What you'll do

• Develop and execute comprehensive SoC verification plans
• Build and maintain verification environments using UVM/OVM/VMM
• Develop testbenches including stimulus, monitors, constraints, assertions, and scoreboards
• Debug simulation failures and perform root-cause analysis
• Collaborate with design and architecture teams on issue resolution

What you need

• 8–14 yrs of experience
• UVM
• Verilog
• Root cause analysis
• VLSI
• B.Tech or B.E.