Sr Engineer CAD Pre-Silicon Front End - Bangalore

About the role

from a blank sheet. The automation our design and verification engineers use to get from RTL to a clean handoff shapes how fast that silicon comes together. You will own the front end automation that carries our silicon from RTL entry to a clean handoff into DFT and implementation. The scope covers RTL design flows, verification

What you'll do

• Own the RTL design flows including build, lint, CDC and formal checks
• Own register generation and the generator driven flows behind interfaces and integration
• Own the DV flows including testbench build, regression execution and coverage collection
• Own emulation and FPGA prototyping build and bring up
• Build and deploy AI assisted tooling across design and verification workflows, working with CAD and Engineering Infrastructure on compute and model access

What you need

• Verilog
• Python
• Linux
• Dashboarding
• Grafana
• FPGA
• Any graduate

Good to have

• UVM
• LLMs
• VLSI
• Prototyping