R&D Engineering, Staff Engineer- 17521

About the role

Sr Engineer - Physical Design & Signoff (Synthesis to GDS2) Sr Engineer - Physical Design & Signoff (Synthesis to GDS2)

What you'll do

• Conceptualizing, designing, and productizing state-of-the-art RTL to GDS implementation for SLM monitors using ASIC design flows
• Designing on-chip Process, Voltage, Temperature, glitch, and Droop monitors for silicon biometrics and reliability
• Executing digital backend activities, including synthesis, pre-layout STA, SDC constraints development, floor planning, bump placement, power planning
• Driving post-layout STA, timing and functional ECO development, and timing signoff methodology for high-frequency IP design closure
• Performing physical verification tasks such as DRC, LVS, PERC, ERC, Antenna, EMIR, and Power signoff

What you need

• 3–6 yrs of experience
• VLSI
• Circuit design
• Perl
• Travel booking
• B.Tech or B.E. or M.Tech or B.Sc or M.Sc