Sr. Logic Engineer

About the role

Pune, Maharashtra, India | FPGA & High-Speed Protocol Interfaces We are seeking a Staff Logic Engineer to architect, implement, and deliver complex FPGA-based logic for high-speed protocol analysis and test systems. The role combines hands-on RTL development, transceiver and interface integration, verification, lab debug, and technical leadership across PCI Express (PCIe), Compute Express Link (CXL), Ethernet, and USB solutions.

What you'll do

• FPGA Architecture and RTL Design
• Own FPGA architecture and microarchitecture for protocol capture, packet processing, filtering, triggering, traffic generation, timestamping, and data movement
• Design, implement, and maintain synthesizable RTL using SystemVerilog, Verilog, or VHDL for high-throughput, low-latency datapaths and control logic
• Integrate and customize FPGA IP for PCIe, CXL, Ethernet, USB, DDR memory, DMA, and other high-speed interfaces
• Develop robust clocking, reset, clock-domain crossing, and data-path schemes across multiple clock domains and transceiver interfaces

What you need

• 8–14 years in software engineering
• FPGA
• Verilog
• VLSI
• Test cases
• Arbitration
• UVM
• B.Tech or B.E. or M.Tech

Good to have

• Python
• Git
• C++
• C
• Prototyping
• Regression testing