Sr Principal Design Engineer

About the role

We are seeking a highly skilled RTL Design Engineer with deep expertise in PCIe protocol (Gen4/Gen5/Gen6) to join our PCIe Controller IP development team. The candidate will be responsible for designing, implementing, and verifying RTL for PCIe controllers and related subsystems, ensuring compliance with protocol standards and performance targets.

What you'll do

• Architect and implement RTL for PCIe IP blocks
• Collaborate with system architects to define micro-architecture and design specifications
• Responsible for the quality of Design Quality. Expertise in LINT/CDC, Synthesis is Must
• Work closely with verification teams to develop testbenches and validate functionality
• Participate in interoperability testing

What you need

• Verilog
• VLSI
• B.Tech or B.E.