Senior Engineer IP
Eaton·Pune
- Can I apply
- Open to any education · Senior level
- Pay
- Pay not stated
- Source
- From the company's careers page · today
- How to apply
- On Eaton's site: account needed, ~10–15 min
Early: posted 6 h ago on their own site
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About the role
Sr Principal Design Engineer at Cadence. Complete DFT ownership of projects including.
What you'll do
- Identifying and implementing RTL changes for DFT
- Performing scan insertion, LEC checks, low power CLP checks
- Developing timing constraints for test mode timing closure
- Scan and ATPG for different fault models
- Boundary scan, ACJTAG, IEEE 1500 implementation and verification
What you need
- 10–15 yrs of experience
- Any graduate
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