Sr Staff ASIC Verification Engineer

About the role

Sr Staff ASIC Verification Engineer at Synopsys (incl. Ansys). Own verification for a major IP block, subsystem, or cross-IP methodology from architecture definition through final signoff and customer delivery.

What you'll do

• Own verification for a major IP block, subsystem, or cross-IP methodology from architecture definition through final signoff and customer delivery
• Define verification strategy, planning, architecture, and signoff criteria for complex IP projects including Ethernet, USB, and similar industry-standard protocols
• Lead technical execution across verification teams by setting objectives, tracking milestones, managing risk, and driving coverage and quality closure
• Apply AI-assisted verification techniques to intelligent debug, regression analytics, test generation
• Build and drive reusable verification infrastructure, UVM environments, and methodology improvements that scale across multiple IP domains and projects

What you need

• 8–14 yrs of experience
• UVM
• Verilog
• B.Tech or B.E.