Sr. Staff Digital Verification Engineer (Memory Interface IP- HBM/DDR/LPDDR)

About the role

Sr. Staff Digital Verification Engineer (Memory Interface IP- HBM/DDR/LPDDR) at Synopsys (incl. Ansys). Design and build verification environments for Interface IP protocols including HBM, DDR, LPDDR, and AMBA using SystemVerilog and UVM.

What you'll do

• Design and build verification environments for Interface IP protocols including HBM, DDR, LPDDR, and AMBA using SystemVerilog and UVM
• Write detailed test plans that cover functional scenarios, corner cases, and protocol compliance for memory controller and interface IP designs
• Develop reusable verification IP and testbenches that can be adapted across multiple projects and IP variants
• Work directly with design and architecture teams to identify bugs, clarify specifications, and close coverage gaps before tapeout
• Run functional coverage analysis, track metrics, and drive coverage closure across complex multi-protocol environments

What you need

• 6–8 yrs of experience
• UVM
• Verilog
• Test cases
• M.Tech or B.Tech or B.E.