Sr. Staff Engineer - Design Formal Verification

About the role

As a Senior Staff Hardware Engineer in Design formal Verification, you will own and drive the strategies to verify complex modules under different functional domains like instruction fetch, branch predictions, Instruction execution pipelines etc.

What you'll do

• Identify blocks suitable for applying Formal Verification
• Create Formal Test-plan for blocks identifying properties to be implemented and sign-off metrics
• Implementation and maintenance of Formal Verification environments in Chisel
• Applying various FV techniques to reduce complexity and prove correctness of DUT
• Debugging RTL to identify causes of failure scenarios

What you need

• 10–18 yrs of experience
• Verilog
• Test cases
• Any graduate