Sr. Staff Engineer - Design Verification

About the role

As a Senior Staff Hardware Engineer in Design Verification, you will own verification strategy and execution for complex SoC / IP blocks, driving quality from architecture through tape‑out. You will define methodology, lead test plan creation, guide junior engineers, and be a key technical partner to architecture, design, and validation teams.

What you'll do

• Own verification for one or more complex subsystems (CPU/LSU/cache/interconnect/IP blocks)
• Define verification strategy, methodology, and test plans from spec/architecture documents
• Ensure coverage closure (functional, code, assertion, and scenario coverage) to sign‑off criteria
• Testbench Architecture & Implementation
• Architect and implement constrained‑random, coverage‑driven testbenches (System Verilog/UVM or equivalent)

What you need

• 10–18 yrs of experience
• UVM
• Verilog
• FPGA
• Test cases
• Prototyping
• B.Sc or M.Sc or PhD or B.Tech or B.E.