Sr/Staff Engineer, Design Verification,System IP

About the role

We are looking for a highly skilled and motivated Senior Design Verification Engineer to join our team. In this role, you will be responsible for the end-to-end verification of our IOMMU (Input/Output Memory Management Unit) IP. You will play a critical role in ensuring the functional correctness and performance of the design, taking ownership of the verification process right from the initial specification understanding down to final coverage closure.

What you'll do

• Be responsible for the end-to-end verification of our IOMMU (Input/Output Memory Management Unit) IP
• Play a critical role in ensuring the functional correctness and performance of the design

What you need

• UVM
• Verilog
• Python
• Machine learning
• Perl
• Bash
• Any graduate