Sr Staff High-Speed Interface Verification Engineer

About the role

Sr Staff High-Speed Interface Verification Engineer at Synopsys (incl. Ansys). Lead verification of high-speed SerDes IP using UVM and SystemVerilog testbenches in mixed-signal co-simulation environments.

What you'll do

• Lead verification of high-speed SerDes IP using UVM and SystemVerilog testbenches in mixed-signal co-simulation environments
• Define, track, and execute verification test plans for PCIE, Ethernet, USB3.1, and other high-speed protocols from architecture through tapeout
• Debug simulation failures across digital and analog domains, working directly with waveform viewers, mixed-signal simulators, and protocol analyzers
• Build and extend UVM testbenches with constrained random sequences, coverage models, and checkers that target real-world corner cases
• Collaborate daily with digital, analog, and mixed-signal design teams to align verification strategy with design intent and silicon bring-up realities

What you need

• 7–13 yrs of experience
• UVM
• Verilog
• Test cases
• B.Tech or B.E. or M.Tech