Sr Staff Mixed-Signal Verification Engineer

About the role

Sr Staff Mixed-Signal Verification Engineer at Synopsys (incl. Ansys). Own end-to-end AMS verification strategy, test plans, coverage models, and sign-off for mixed-signal blocks and subsystems across complex IP projects.

What you'll do

• Own end-to-end AMS verification strategy, test plans, coverage models, and sign-off for mixed-signal blocks and subsystems across complex IP projects
• Build and maintain UVM/SystemVerilog verification environments that integrate seamlessly with Verilog-A, Verilog-AMS behavioral models, and mixed-signal simulators
• Debug complex analog-digital interface issues, simulation convergence problems, and cross-domain failures using waveform analysis and AMS-specific debug tools
• Develop assertions, monitors, scoreboards, and automated verification infrastructure that catch real bugs, not just check boxes
• Drive AMS simulation efficiency improvements, optimize regression flows, and reduce debug turnaround time across the verification pipeline

What you need

• 8–14 yrs of experience
• Verilog
• UVM
• Python
• Test cases
• Machine learning
• Perl
• Any graduate