Sr Staff /Staff DFT Engineer

About the role

You will lead end-to-end Design for Testability (DFT) implementation, verification for complex ASIC/SoC designs. You will own all aspects of DFT for SoC such as MBIST, IJTAG, Scan and ATPG . You will also contribute significantly to DFT methodologies to establish flow for all DFT features like MBIST,SCAN and ATPG and enable first-pass success of these chips.

What you'll do

• Pre-Silicon test planning & verification strategy
• Adept at root cause analysis and resolving DFT implementation issues
• Experience working at startups
• Working with ATE (Automatic Test Equipment) for bring-up, debugging, and yield improvement
• Proficiency in Synopsys (TetraMAX/DFT Compiler) or Siemens/Mentor (Tessent) tools, Verilog/SystemVerilog

What you need

• 8–14 yrs of experience
• Verilog
• VLSI
• Circuit design
• Python
• Root cause analysis
• Perl
• B.Sc or M.Sc or PhD