STA / Synthesis Engineer (Staff / Sr. Staff / Principal)

About the role

As a Staff/Sr. Staff/Principal STA/Synthesis Engineer at Velaura AI, you will own RTL-to-gate synthesis, static timing analysis, and timing closure for next-generation AI and high-performance computing silicon. You will be responsible for driving implementation quality, timing convergence, power optimization, and sign-off readiness

What you'll do

• Drive RTL-to-gate synthesis for complex compute, CPU, VPU, AI accelerator, and low-power cores using industry-standard synthesis tools
• Own synthesis setup, constraints, optimization, quality checks, and netlist delivery for block-level and subsystem-level designs
• Lead static timing analysis and timing closure activities across multiple modes, corners, voltage domains, and clock domains
• Optimize designs for timing, power, area, and cost while meeting aggressive design targets and schedule requirements
• Develop, validate, and maintain high-quality timing constraints, including full-chip, block-level, generated clock, false path, multicycle path, and interface constraints

What you need

• 5–15 yrs of experience
• Python
• Perl
• VLSI
• B.Tech or B.E.