Staff CPU Design Verification Engineer

About the role

As a Staff Hardware Engineer in Design Verification of CPU, you will own verification strategy and execution for complex out‑of‑order (OOO) processor and cache/memory subsystems . You will define methodology, lead testplan creation, and drive verification of speculative execution, memory ordering, and coherence features from architecture through tape‑out.

What you'll do

• Back‑end: scheduler/issue queues, execution units, bypass networks
• Good knowledge on execution pipelines and multiple execution pipeline scenarios
• Memory consistency model (e.g. RVWMO, TSO) and ordering rules
• Coherence/consistency interactions across multi‑core systems
• Drive coverage closure (functional, code, assertion, and scenario coverage) to sign‑off criteria

What you need

• 8–14 yrs of experience
• UVM
• Verilog
• Test cases
• B.Sc or M.Sc or PhD or B.Tech or B.E.