Staff Design Verification

About the role

We are looking for a Staff Design Verification Engineer to lead the verification of complex out‑of‑order (OOO) CPU cores and memory subsystems . In this role you will own verification strategy, methodology, and execution for major core blocks, drive coverage and sign‑off, and act as a technical leader and mentor within the DV team.

What you'll do

• Front‑end: fetch, branch prediction, instruction decode
• Rename / register mapping and dependency tracking
• Issue queues / schedulers, execution units, bypass networks
• Load‑store unit (LSU), store buffer, atomics/LR‑SC, fences, speculative loads/stores
• Translate ISA + micro‑architecture specifications into detailed verification plans and test strategies

What you need

• 8–14 yrs of experience
• UVM
• Verilog
• B.Sc or M.Sc or PhD or B.Tech or B.E.