Staff Digital Verification Engineer

About the role

These products integrate digital control, telemetry, fault management, communication interfaces, configurable peripherals, and advanced power-control functions for AI, datacenter, enterprise computing, networking, and high-performance power delivery applications. You will independently own verification of significant blocks and features from planning through closure.

What you'll do

• Own verification of complex digital blocks or major SoC features from requirements analysis through coverage closure
• Develop feature-based verification plans from product, architecture, and microarchitecture specifications; identify gaps, ambiguities, corner cases, and risks
• Build and extend reusable SystemVerilog/UVM environments, including sequences, monitors, scoreboards, checkers, assertions, and coverage models
• Develop constrained random and targeted tests for normal operation, error handling, recovery, and system-level interactions
• Drive functional, code, toggle, FSM, and assertion coverage closure using regression and coverage data

What you need

• UVM
• Verilog
• Python
• Test cases
• Linux
• Bash
• B.Tech or B.E. or M.Tech

Good to have

• Perl