Staff Electrical Engineer

About the role

If you are looking for a challenging and exciting career in the world of technology, then look no further.

What you'll do

• Work with a dedicated team of engineers, using the latest verification practices, to verify the digital design intent of our SOC's at the block and system level
• Engage early in the verification process to understand the verification requirements and participate in UVM or SystemVerilog testbench development
• Responsible for creating tests to verify the SOC design at the system or block level and to implement checking mechanisms to ensure coverage closure
• 8+ years (BSEE), 6+ years (MSEE), or 3+ years (PhD) of relevant industry experience
• Expertise in developing testbenches using System Verilog and UVM

What you need

• 8–14 yrs of experience
• Verilog
• UVM
• Python
• Test cases
• Bash
• Any graduate