Staff Engineer Design

About the role

Develop and execute comprehensive verification plans for WLAN MAC digital designs and subsystems. Build, enhance, and maintain System Verilog/UVM-based verification environments and testbenches. Create test plans, verification scenarios, and functional tests for WLAN MAC protocols. Develop and integrate Verification IP (VIP) for industry-standard interfaces such as AXI, AHB, APB, and PCIe.

What you'll do

• Work with industry-leading verification methodologies, System Verilog/UVM
• Develop and execute comprehensive verification plans for WLAN MAC digital designs and subsystems
• Build, enhance, and maintain System Verilog/UVM-based verification environments and testbenches
• Create test plans, verification scenarios, and functional tests for WLAN MAC protocols
• Develop and integrate Verification IP (VIP) for industry-standard interfaces such as AXI, AHB, APB, and PCIe

What you need

• 5–9 yrs of experience
• UVM
• Verilog
• Test cases
• Customer success
• B.Tech or B.E. or M.Tech