Staff Engineer Design

About the role

If you have expertise in ASIC/FPGA design, SystemVerilog, Python automation, and FPGA prototyping , this is an opportunity to shape innovative semiconductor solutions while collaborating with global engineering teams. Your role Key responsibilities in your new role Develop Real Number Models (RNM) using SystemVerilog and svreal for Analog/Mixed-Signal IP modeling.

What you'll do

• Develop Real Number Models (RNM) using SystemVerilog and svreal for Analog/Mixed-Signal IP modeling
• Build and maintain FPGA-based prototypes for SoC and system-level validation
• Drive pre- and post-silicon firmware validation on FPGA platforms
• Create Python automation frameworks for simulation, FPGA flows, and CI/CD
• Lead FPGA modeling architecture and mentor engineering teams

What you need

• FPGA
• Verilog
• Python
• Prototyping
• CI/CD
• Data privacy
• PhD or B.Tech or B.E. or Chartered Accountant

Good to have

• Compensation and benefits
• Customer success