Staff Engineer Design

About the role

Candidate will be leading/involved in planning the modelling of analog /hard IP by means of Verilog and system Verilog. He is also expected to take part of development of modelling support pre-silicon validation.

What you'll do

• Key responsibilities in your new role

What you need

• 6–11 yrs of experience
• Verilog
• UVM
• Customer success
• B.Sc or M.Sc or B.Tech or B.E.