Staff Engineer - ESD Design

About the role

Responsibilities will include, but are not limited to ESD Architecture Leadership & Strategy Define and own ESD architecture and protection strategy for high-speed I/O portfolios including: HBM (High Bandwidth Memory) / DDR / LPDDR PHY I/Os PCIe, USB, Ethernet, MIPI, and proprietary interfaces Lead ESD–I/O co‑design trade‑off decisions, balancing: Aggressive ESD targets (HBM / CDM / MM).Ultra‑low capacitance and leakage requirements

What you'll do

• Lead ESD–I/O co‑design trade‑off decisions, balancing: Aggressive ESD targets (HBM / CDM / MM).Ultra‑low capacitance and leakage requirements
• Drive architectural choices for: Snapback clamps, rail clamps, diode steering networks. Triggered and advanced ESD devices (technology‑dependent). Domain isolation and…
• Establish simulation methodologies for: Transient ESD stress (TLP‑equivalent behavior). Dynamic clamp triggering and current handling. I/O performance impact (cap…
• Own ESD modeling correlation: Work with device/modeling teams on compact models (dynamic R, triggering, CV behavior)
• Drive correlation between SPICE simulations, TLP/VF‑TLP, and silicon results

What you need

• 8–14 yrs of experience
• Circuit design
• VLSI
• Root cause analysis
• B.Tech or B.E. or M.Tech or PhD