Staff Engineer IP Verification - Digital Design Verification

About the role

Complete ownership of verification and end to end analysis of complex block level custom designs with advanced low power and power management technologies spread across multiple categories such as DDR5, LPDDR5, DDR6 and LPDDR6 that are capable of operating at high speeds of up to 11,4000MT/s. At the Staff level, engineers are expected to:

What you'll do

• Understand design specifications and define verification scope, strategy, and plans for block/chip RTL verification
• Develop, execute, and maintain verification testbenches and test vectors using digital simulation tools and methodologies (SV-UVM)
• Run directed and constrained-random tests and regressions; analyze results and triage failures
• Close verification metrics (functional coverage / code coverage as applicable) and identify verification holes to demonstrate readiness toward tapeout
• Provide verification support to design projects by simulating, analyzing

What you need

• 7–9 yrs of experience
• UVM
• Python
• Test cases
• Perl
• B.Tech or B.E.