Staff Engineer – STA Methodology/CAD

About the role

We are seeking a highly motivated Staff Engineer – STA Methodology to drive the development, deployment, and enhancement of next-generation Static Timing Analysis (STA) methodologies for complex SoCs. The ideal candidate will have strong expertise in timing signoff, constraint methodologies, automation, and timing closure flows across advanced technology nodes.

What you'll do

• Define, develop, and improve STA methodologies for block, subsystem, and full-chip designs
• Drive timing signoff flows including MMMC analysis, constraint validation, ECO methodologies, and correlation strategies
• Develop automation and infrastructure using Tcl/Python/Perl to improve timing analysis efficiency and turnaround time
• Own methodology development for timing closure, reporting, constraint management, and signoff quality metrics
• Collaborate closely with RTL, Synthesis, Physical Design, DFT, and CAD teams to enable robust timing convergence

What you need

• 7–13 yrs of experience
• VLSI
• Python
• Perl
• B.Sc or B.Tech or B.E. or BCA or M.Sc or M.Tech or MCA

Good to have

• Machine learning